circuit Booth :
  module Booth :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip x : UInt<16>, flip y : UInt<16>, busy : UInt<1>, flip start : UInt<1>, z : UInt<32>}

    reg yReg : UInt<17>, clock with :
      reset => (reset, UInt<17>("h0")) @[Booth.scala 11:21]
    reg sumReg : SInt<32>, clock with :
      reset => (reset, asSInt(UInt<32>("h0"))) @[Booth.scala 12:23]
    reg cnt : UInt<8>, clock with :
      reset => (reset, UInt<8>("h0")) @[Booth.scala 13:20]
    reg state : UInt<2>, clock with :
      reset => (reset, UInt<2>("h0")) @[Booth.scala 17:22]
    wire nextState : UInt<2> @[Booth.scala 18:23]
    node _T = mux(io.start, UInt<2>("h1"), UInt<2>("h0")) @[Booth.scala 20:21]
    node _T_1 = eq(cnt, UInt<4>("hf")) @[Booth.scala 21:29]
    node _T_2 = mux(_T_1, UInt<2>("h2"), UInt<2>("h1")) @[Booth.scala 21:24]
    node _nextState_T = eq(UInt<2>("h0"), state) @[Mux.scala 81:61]
    node _nextState_T_1 = mux(_nextState_T, _T, UInt<2>("h0")) @[Mux.scala 81:58]
    node _nextState_T_2 = eq(UInt<2>("h1"), state) @[Mux.scala 81:61]
    node _nextState_T_3 = mux(_nextState_T_2, _T_2, _nextState_T_1) @[Mux.scala 81:58]
    node _nextState_T_4 = eq(UInt<2>("h2"), state) @[Mux.scala 81:61]
    node _nextState_T_5 = mux(_nextState_T_4, UInt<2>("h0"), _nextState_T_3) @[Mux.scala 81:58]
    nextState <= _nextState_T_5 @[Booth.scala 24:13]
    state <= nextState @[Booth.scala 25:9]
    io.busy <= UInt<1>("h0") @[Booth.scala 27:11]
    io.z <= UInt<1>("h0") @[Booth.scala 28:8]
    reg xReg : SInt<32>, clock with :
      reset => (reset, asSInt(UInt<32>("h0"))) @[Booth.scala 29:21]
    reg lastResultReg : UInt<32>, clock with :
      reset => (reset, UInt<32>("h0")) @[Booth.scala 31:30]
    node _T_3 = eq(UInt<2>("h0"), state) @[Booth.scala 47:17]
    when _T_3 : @[Booth.scala 47:17]
      cnt <= UInt<1>("h0") @[Booth.scala 49:11]
      wire _xReg_WIRE : SInt<16> @[Booth.scala 50:28]
      node _xReg_T = asSInt(io.x) @[Booth.scala 50:28]
      _xReg_WIRE <= _xReg_T @[Booth.scala 50:28]
      xReg <= _xReg_WIRE @[Booth.scala 50:12]
      io.z <= lastResultReg @[Booth.scala 51:12]
      sumReg <= asSInt(UInt<1>("h0")) @[Booth.scala 52:14]
      node _yReg_T = dshl(io.y, UInt<1>("h1")) @[Booth.scala 53:20]
      yReg <= _yReg_T @[Booth.scala 53:12]
    else :
      node _T_4 = eq(UInt<2>("h1"), state) @[Booth.scala 47:17]
      when _T_4 : @[Booth.scala 47:17]
        node _T_5 = bits(yReg, 1, 0) @[Booth.scala 33:22]
        lastResultReg <= UInt<1>("h0") @[Booth.scala 57:21]
        node _T_6 = bits(yReg, 1, 0) @[Booth.scala 33:22]
        node _T_7 = asUInt(xReg) @[Booth.scala 64:14]
        node _T_8 = sub(asSInt(UInt<1>("h0")), xReg) @[Booth.scala 65:10]
        node _T_9 = tail(_T_8, 1) @[Booth.scala 65:10]
        node _T_10 = asSInt(_T_9) @[Booth.scala 65:10]
        node _T_11 = asUInt(_T_10) @[Booth.scala 65:17]
        node _T_12 = bits(reset, 0, 0) @[Booth.scala 58:13]
        node _T_13 = eq(_T_12, UInt<1>("h0")) @[Booth.scala 58:13]
        when _T_13 : @[Booth.scala 58:13]
          printf(clock, UInt<1>("h1"), "[%d state=%b], yReg=%b, yRegLast=%b, x=%b, -x=%b\n", cnt, state, yReg, _T_6, _T_7, _T_11) : printf @[Booth.scala 58:13]
        node _T_14 = bits(yReg, 1, 0) @[Booth.scala 33:22]
        node _T_15 = sub(asSInt(UInt<1>("h0")), xReg) @[Booth.scala 67:75]
        node _T_16 = tail(_T_15, 1) @[Booth.scala 67:75]
        node _T_17 = asSInt(_T_16) @[Booth.scala 67:75]
        node _T_18 = eq(UInt<1>("h1"), _T_14) @[Mux.scala 81:61]
        node _T_19 = mux(_T_18, xReg, asSInt(UInt<1>("h0"))) @[Mux.scala 81:58]
        node _T_20 = eq(UInt<2>("h2"), _T_14) @[Mux.scala 81:61]
        node _T_21 = mux(_T_20, _T_17, _T_19) @[Mux.scala 81:58]
        wire _add_WIRE : SInt<32> @[Booth.scala 36:32]
        node _add_T = asUInt(_T_21) @[Booth.scala 36:32]
        node _add_T_1 = asSInt(_add_T) @[Booth.scala 36:32]
        _add_WIRE <= _add_T_1 @[Booth.scala 36:32]
        node add = dshl(_add_WIRE, cnt) @[Booth.scala 36:54]
        node _sumReg_T = add(sumReg, add) @[Booth.scala 37:22]
        node _sumReg_T_1 = tail(_sumReg_T, 1) @[Booth.scala 37:22]
        node _sumReg_T_2 = asSInt(_sumReg_T_1) @[Booth.scala 37:22]
        sumReg <= _sumReg_T_2 @[Booth.scala 37:12]
        node _yReg_T_1 = dshr(yReg, UInt<1>("h1")) @[Booth.scala 38:18]
        yReg <= _yReg_T_1 @[Booth.scala 38:10]
        node _T_22 = asUInt(sumReg) @[Booth.scala 43:14]
        node _T_23 = bits(reset, 0, 0) @[Booth.scala 39:11]
        node _T_24 = eq(_T_23, UInt<1>("h0")) @[Booth.scala 39:11]
        when _T_24 : @[Booth.scala 39:11]
          printf(clock, UInt<1>("h1"), "yRegExtra = %b, addValue = %b, sum = %b\n", yReg, add, _T_22) : printf_1 @[Booth.scala 39:11]
        node _cnt_T = add(cnt, UInt<1>("h1")) @[Booth.scala 68:18]
        node _cnt_T_1 = tail(_cnt_T, 1) @[Booth.scala 68:18]
        cnt <= _cnt_T_1 @[Booth.scala 68:11]
        io.busy <= UInt<1>("h1") @[Booth.scala 69:15]
      else :
        node _T_25 = eq(UInt<2>("h2"), state) @[Booth.scala 47:17]
        when _T_25 : @[Booth.scala 47:17]
          cnt <= UInt<1>("h0") @[Booth.scala 72:11]
          node result = asUInt(sumReg) @[Booth.scala 73:27]
          io.z <= result @[Booth.scala 74:12]
          node _T_26 = bits(reset, 0, 0) @[Booth.scala 75:13]
          node _T_27 = eq(_T_26, UInt<1>("h0")) @[Booth.scala 75:13]
          when _T_27 : @[Booth.scala 75:13]
            printf(clock, UInt<1>("h1"), "result = %b\n", result) : printf_2 @[Booth.scala 75:13]
          lastResultReg <= result @[Booth.scala 76:21]

